00-计算机系统概述

基本构成

• CPU
  • PC
  • IR
  • Execution unit
  • MAR: Memory address register
  • MBR: Memory buffer register
  • I/O AR
  • I/O BR
• I/O Module
  • Buffers
• Main Memory
  • Instruction
  • Data
• System Bus

指令

指令周期

• Basic Instruction Cycle
  1. Start
  2. Fetch Next Instruction (Fetch Cycle)
  3. Execute Instruction (Execute Cycle, then goto Fetch stage)
  4. HALT

中断

• No interrupts
• Interrupts: short I/O wait
• Interrupts: long I/O wait

中断和指令周期

• 加入中断的指令周期
  1. START
  2. Fetch Next Instuction (fetch cycle)
  3. Execute Instruction (execute cycle)
     1. if interrupts disabled, jump to 2
     2. if interrupts enabled, jump to 4
     3. or HALT
  4. Check for interrupt; Service interrupt (interrupt cycle)

中断处理

• 中断的典型处理顺序，
• 涉及软硬件协作，硬件负责处理 PC 和 PSW；
  • Hardware
    1. Device controller or other system hardware issues an interrupt
    2. Processor finishes execution of current instruction
    3. Processor signals acknowledgment of interrupt
    4. Processor pushes PSW and PC onto control stack
    5. Processor loads new PC value based on interrupt
  • Software
    1. Save remainder of process state infomation
    2. Process interrupt
    3. Restore process state information
    4. Restore old PSW and PC

多中断处理

• 顺序处理和嵌套处理；

存储器层次结构

• Processor
  • CPU: processor register
  • Cache: L1, L2, L3
• SD-RAM DDR-SDRAM
  • Physical memory: RAM
• Solid State Drives
  • Non-volatile flash-based memory
• Mechanical Hard Drives (Virtual Memory)
  • File-based memory

高速缓存

高速缓存结构

高速缓存读操作

高速缓存设计考虑因素

高速缓存大小

块大小

映射函数

置换算法

写策略

高速缓存级数

直接内存存取(DMA)

Transclude of 60-IO管理与磁盘#dma-工作流程

多处理器与多核计算机

对称多处理器SMP